1. Field of the Invention
The present invention relates to chemical mechanical polishing slurries for semiconductor integrated circuit substrates. Specifically, this invention is a CMP slurry having a unique chemistry that is especially suitable for chemical mechanical planarization where a high silicon dioxide removal rate and a low silicon nitride removal rate are required on the same substrate.
2. Description of the Related Art
Integrated circuits (IC) are made up of millions of active devices formed in or on a silicon substrate. The active devices form functional circuits and components. These devices are then connected by the use of multilevel metallized interconnects and vias. Interconnection structures normally have a first layer metallization, an interconnect plug, a second layer of metallization, and sometimes a third or more layers of metallization with their respective interconnects. Inter level dielectrics (ILDs), such as doped and undoped SiO2, are used to electrically isolate the different levels of interconnections.
Shallow trench isolation (STI) is a technology for device isolation in a give layer in the IC manufacturing process. In the STI process, silicon nitride is deposited on thermally grown oxide. After deposition of the nitride, a shallow trench is etched into the substrate using a mask. A layer of oxide is then deposited into the trench so that the trench forms an area of insulated dielectric that acts to isolate the devices in a chip and, thus, reduces the cross-talk between active devices. The excess deposited oxide must be polished off and the trench planarized to prepare for the next level of metallization. Silicon nitride is applied to the silicon to prevent polishing of the masked silicon oxide of the device.
In a typical mechanical polishing process, the substrate is placed in direct contact with a rotating polishing pad. A carrier applies pressure against the backside of the substrate. During the polishing process, the pad and table are rotated while a downward force is maintained against the substrate back. An abrasive and chemically reactive solution, commonly referred to as “CMP slurry”, is flowed onto the pad during polishing. The chemicals and abrasive particles in the slurry initiate the polishing process by interacting with the wafer being polished. As slurry is provided to the wafer/pad interface, and the polishing process is facilitated by the rotational movement of the pad relative to the substrate. Polishing is continued in this manner until the final desired film thickness is achieved by removal of the required amount of thin-film material.
When polishing oxides, it is desirable that the slurry have a high removal rate towards the oxide layer and a low removal rate towards other layers that may be exposed during CMP. A polishing slurry should be tailored to provide effective polishing at the desired polishing ranges selective to specific thin layer materials, while at the same time minimizing surface imperfections, defects, corrosion, erosion and the removal of silicon nitride and other stop layers.
CMP slurries useful for polishing oxides typically contain an abrasive at an alkaline or high pH. These slurries either rely on potassium hydroxide or ammonium hydroxide to effectively buffer the high pH. While these slurries polish silica at high rates, they also polish silicon nitride at high rates. Typically, the ratio of these removal rates, i.e., the selectivity is, at most, about 5 to 1 silicon oxide to silicon nitride. It is believed that the mechanism of silicon nitride polishing is oxidative hydrolysis of the nitride to the oxide in an aqueous environment. At an alkaline pH this oxide and nitride are similarly etched at a high rate. Thus, present CMP slurries undesirably polish silicon nitride at an unacceptably high rate.
There remains a need in the semiconductor industry for CMP slurries that have greater than a 5 to 1 oxide to nitride selectivity ratio. Accordingly, new CMP slurries that selectively remove the oxide at high rates while leaving the stop layer of silicon nitride relatively intact, while increasing the output and reducing the costs of the CMP process are needed to overcome the present manufacturing problems. This is because a low selectivity process, when used in a manufacturing environment, will necessarily suffer overpolishing—in thinner film parts of the wafer—and the nitride stop layer will not prevent breakthrough to the underlying thin film(s).